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1 radiation hardened and see hardened 6a synchronous buck regulator ISL70001SEH, isl70001srh the ISL70001SEH, isl70001srh are radiation hardened and see hardened high efficiency monolithic synchronous buck regulators with integrated mosfets. this single chip power solution operates over an input voltage range of 3v to 5.5v and provides a tightly regulated output voltage that is externally adjustable from 0.8v to ~85% of the input voltage. output load current capacity is 6a for t j < +145c . high integration and class leading radiation tolerance makes the ISL70001SEH, isl70001srh ideal choices to power many of today?s small form factor a pplications. two devices can be synchronized to provide a complete power solution for large scale digital ics, like field pr ogrammable gate arrays (fpgas) that require separate core and i/o voltages. applications ? fpga, cpld, dsp, cpu core or i/o voltages ? low-voltage, high-density distributed power systems related literature ? isl70001srheval1z evaluation board, an1518 ? single event effects (see) testing of the isl70001srh synchronous buck regulator ? total dose testing of the isl70001srh hardened point of load regulator features ? 1% reference voltage over line, load, temperature and radiation ? current mode control for excellent dynamic response ? full mil-temp range operation (t a = -55c to +125c) ? high efficiency > 90% ? fixed 1mhz operating frequency ? available in a thermally enhanced heatsink package - r48.b ? operates from 3v to 5.5v supply ? adjustable output voltage - two external resistors set v out from 0.8v to ~85% of v in ? bi-directional sync pin allows two devices to be synchronized 180 out-of-phase ? starts into pre-biased load ? power-good output voltage monitor ? adjustable analog soft-start ? input undervoltage, output undervoltage and output overcurrent protection ? electrically screened to dla smd 5962-09225 ? qml qualified per mil-prf-38535 requirements ? eh version is wafer-by-wafer acceptance tested for eldrs ?radiation hardness - total dose [50-300rad(si)/s] . . . . . . . . . 100krad(si) (min) - total dose [<10mrad(si)/s]. . . . . . . . . . . . 50krad(si) (min) ? see hardness - sel and seb let eff . . . . . . . . . . . 86.4mev/mg/cm 2 (min) -sefi x-section (let eff = 86.4mev/mg/cm 2 ) 1.4 x 10 -6 cm 2 (max) -set let eff (< 1 pulse perturbation) 86.4mev/mg/cm 2 (min) figure 1. typical application figure 2. ef ficiency 5v input to 3.3v output, t a = +25c ISL70001SEH isl75051seh ISL70001SEH 5v supply core aux i/o rad tolerant fpga synch synch load current (a) efficiency (%) 70 75 80 85 90 95 0123456 february 24, 2014 fn7956.2 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2011, 2013, 2014. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
ISL70001SEH, isl70001srh 2 fn7956.2 february 24, 2014 submit document feedback functional block diagram power-on reset (por) pwm reference 0.6v soft start compensation ea gm slope compensation gate drive current sense lxx pvinx control logic pwm fb uv pgood power-good pgndx avdd ss m/s sync porsel ref tdi tdo bit zap trim agnd dvdd dgnd en trim
ISL70001SEH, isl70001srh 3 fn7956.2 february 24, 2014 submit document feedback pin configuration ISL70001SEH, isl70001srh (48 ld cqfp) top view ordering information ordering number (note 2) part number temp. range (c) package (rohs compliant) pkg. dwg. # 5962r0922502vxc ISL70001SEHvf (note 1) -55 to +125 48 ld cqfp r48.a 5962r0922502vyc ISL70001SEHvfe (note 1) -55 to +125 48 ld cqfp with heatsink r48.b 5962r0922502v9a ISL70001SEHvx -55 to +125 die 5962r0922501vxc isl70001srhvf (note 1) -55 to +125 48 ld cqfp r48.a 5962r0922501qxc isl70001srhqf (note 1) -55 to +125 48 ld cqfp r48.a 5962r0922501v9a isl70001srhvx -55 to +125 die isl70001srhf/proto isl70001srhf/proto (note 1) -55 to +125 48 ld cqfp r48.a ISL70001SEHfe/proto ISL70001SEHfe/proto (note 1) -55 to +125 48 ld cqfp with heatsink r48.b isl70001srhx/sample isl70001srhx/sample -55 to +125 die isl70001srheval1z evaluation board isl70001asehev1z evaluation board notes: 1. these intersil pb-free hermetic packaged products employ 100% au plate - e4 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. 2. specifications for rad hard qml devices are controlled by the defense logistics agency land and maritime (dla). the smd numbe rs listed in the ordering information table on must be used when ordering. 7 8 9 10 11 12 13 14 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 15 16 17 18 19 20 21 22 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 pvin3 lx3 pgnd3 pgnd3 pgnd4 pgnd4 lx4 pvin4 pvin4 pvin5 pvin5 lx5 m/s zap tdi tdo pgood dvdd dgnd dgnd agnd agnd ss dvdd sync pvin1 pvin1 lx1 pgnd1 pgnd2 pgnd2 lx2 pvin2 pvin2 pvin3 pgnd1 avdd ref fb en porsel pvin6 pvin6 lx6 pgnd6 pgnd6 pgnd5 pgnd5 * heatsink * heatsink available in r48.b package
ISL70001SEH, isl70001srh 4 fn7956.2 february 24, 2014 submit document feedback pin descriptions pin number pin name description 1, 2, 27, 28, 29, 30, 37, 38, 39, 40, 47, 48 pgndx these pins are the power grounds associated with the corresponding inte rnal power blocks. connect these pins directly to the ground plane. these pins should also co nnect to the negative terminals of the input and output capacitors. locate the input and output capa citors as close as possible to the ic. 3, 26, 31, 36, 41, 46 lxx these pins are the outputs of the corresponding internal power blocks and should be connected to the output filter inductor. internally, these pins are connected to the synchronous mosfet power switches. to minimize voltage undershoot, it is recommended that a schottky diode be connected from th ese pins to pgndx. the schottky diode should be located as close as possible to the ic. 4, 5, 24, 25, 32, 33, 34, 35, 42, 43, 44, 45 pvinx these pins are the power supply inputs to the corr esponding internal power blocks. these pins must be connected to a common power supply rail, which must fall in the range of 3v to 5.5v. bypass these pins directly to pgndx with ceramic capacitors loca ted as close as possible to the ic. 6 sync this pin is the synchronization i/o for the ic. when co nfigured as an output (master mode), this pin drives the sync input of another ISL70001SEH, isl70001srh. when configured as an input (slave mode), this pin accepts the sync output from another ISL70001SEH, isl7 0001srh or an external clock. synchronization of the slave unit is 180 out-of-phase with respect to the ma ster unit. if synchronizing to an external clock, the clock must be see hardened and the frequenc y must be within the range of 1mhz 20%. 7 m/s this pin is the master/slave input for selecting the dire ction of the bi-directional sync pin. for sync = output (master mode), connect this pin to dvdd. for sync = input (slave mode), connect this pin to dgnd. 8 zap this pin is a trim input and is used to adjust various internal circuitry. connect this pin to dgnd. 9 tdi this pin is the test data input of the inte rnal bit circuitry. connect this pin to dgnd. 10 tdo this pin is the test data output of the in ternal bit circuitry. connect this pin to dgnd. 11 pgood this pin is the power-good output. this pin is an open drain logic output that is pulled to dgnd when the output voltage is outside a 11% typical regulation window. this pin can be pulled up to any voltage from 0v to 5.5v, independent of the supply voltage. a nominal 1k ? to 10k ? pull-up resistor is recommended. bypass this pin to dgnd with a 10nf ceramic capacitor to mitigate see. 12 ss this pin is the soft-start input. conne ct a ceramic capacitor from this pin to dgnd to set the soft-start output ramp time in accordance with equation 1: where: t ss = soft-start output ramp time c ss = soft-start capacitor v ref = reference voltage (0.6v typical) i ss = soft-start charging current (23a typical) soft-start time is adjustable from approximately 2ms to 200ms. the range of the soft-start capacitor should be 82nf to 8.2f, inclusive. 13, 14 dvdd these pins are the bias supply in puts to the internal digital control circui try. connect these pins together at the ic and locally filter them to dgnd using a 1 ? resistor and a 1f ceramic ca pacitor. locate both filter components as close as possible to the ic. 15, 16 dgnd these pins are the digital grou nd associated with the internal digita l control circuitry. connect these pins directly to the ground plane. 17, 18 agnd these pins are the analog grou nd associated with the internal analog control circuitry. connect these pins directly to the ground plane. 19 avdd this pin is the bias supply input to the internal analog control circuitry. locally filter this pin to agnd using a 1 ? resistor and a 1f ceramic capacitor. locate both fi lter components as close as possible to the ic. 20 ref this pin is the internal reference voltage output. by pass this pin to agnd with a 220nf ceramic capacitor located as close as possible to the ic. the bypass capaci tor is needed to mitigate see. no current (sourcing or sinking) is available from this pin. t ss c ss v ref ? i ss ? = (eq. 1)
ISL70001SEH, isl70001srh 5 fn7956.2 february 24, 2014 submit document feedback 21 fb this pin is the voltage feedback input to the internal er ror amplifier. connect a resi stor from fb to vout and from fb to agnd to adjust the output voltage in accordance with equation 2: where: v out = output voltage v ref = reference voltage (0.6v typical) r t = top divider resistor (must be 1k ? ) r b = bottom divider resistor the top divider resistor must be 1k ? to mitigate see. connect a 4.7nf ceramic capacitor across rt to mitigate see and to improve stability margins. 22 en this pin is the enable input to the ic. this is a co mparator type input with a rising threshold of 0.6v and programmable hysteresis. driving this pin above 0.6v en ables the ic. bypass this pin to agnd with a 10nf ceramic capacitor to mitigate see. 23 porsel this pin is the input for selecting the rising and falling por (power-on-reset) thresholds. for a nominal 5v supply, connect this pin to dvdd. for a nominal 3.3v supply, connect this pin to dgnd. for nominal supply voltages between 5v and 3.3v, connect this pin to dgnd. heatsink the heatsink is electrically isolated and should be connected to a thermal chassis of any potential which offers optimal thermal relief. pin descriptions (continued) pin number pin name description v out v ref 1r t r b ? ?? + ?? ? = (eq. 2)
ISL70001SEH, isl70001srh 6 fn7956.2 february 24, 2014 submit document feedback typical application schematic figure 3. 5v input supply voltage with master mode synchronization pgood fb 470f 1h 5v 1f pvin1 pvin2 isl70001srh, ISL70001SEH 3a pvin3 1 ? 1k ? 499 ? pvin4 pvin5 pvin6 en m/s porsel sync dvdd dgnd tdo zap tdi 0v to 5.5v vsense 10nf 1f avdd agnd lx1 lx2 lx3 lx4 lx5 lx6 pgnd1 pgnd2 pgnd3 pgnd4 pgnd5 pgnd6 ref 220nf ss 100nf 10nf 1f 100f 20v 1f 1 ? 1.8v 6a
ISL70001SEH, isl70001srh 7 fn7956.2 february 24, 2014 submit document feedback figure 4. 3.3v input supply voltage with slave mode synchronization typical application schematic (continued) pgood fb 470f 1h 1.8v 3.3v 1f pvin1 pvin2 3a pvin3 1 ? 1k ? 499 ? pvin4 pvin5 pvin6 en m/s porsel sync avdd agnd tdo zap tdi 0v to 5.5v vsense 10nf 1f dvdd dgnd lx1 lx2 lx3 lx4 lx5 lx6 pgnd1 pgnd2 pgnd3 pgnd4 pgnd5 pgnd6 ref 220nf ss 100nf 10nf 1f 100f 4.7nf 20v 6a 1f 1 ? isl70001srh, ISL70001SEH
ISL70001SEH, isl70001srh 8 fn7956.2 february 24, 2014 submit document feedback absolute maximum rating s thermal information avdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . agnd - 0.3v to agnd + 6.5v dvdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dgnd - 0.3v to dgnd +6.5v lxx, pvinx . . . . . . . . . . . . . . . . . . . . . . . . . . . pgndx - 0.3v to pgndx + 6.5v avdd - agnd, dvdd - dgnd . . . . . . . . . . . . . . . . . . . . pvinx - pgndx 0.3v signal pins (note 7) . . . . . . . . . . . . . . . . . . . . . agnd - 0.3v to avdd + 0.3v digital control pins (note 8) . . . . . . . . . . . . . . dgnd - 0.3v to dvdd + 0.3v pgood . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .dgnd - 0.3v to dgnd + 6.5v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .dgnd - 0.3v to dgnd + 2.5v absolute maximum ratings (note 9) avdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . agnd - 0.3v to agnd + 5.7v dvdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .dgnd - 0.3v to dgnd + 5.7v lxx, pvinx . . . . . . . . . . . . . . . . . . . . . . . . . . . pgndx - 0.3v to pgndx + 5.7v avdd - agnd, dvdd - dgnd . . . . . . . . . . . . . . . . . . . . pvinx - pgndx 0.3v signal pins (note 7) . . . . . . . . . . . . . . . . . . . . . agnd - 0.3v to avdd + 0.3v digital control pins (note 8) . . . . . . . . . . . . . . dgnd - 0.3v to dvdd + 0.3v pgood . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .dgnd - 0.3v to dgnd + 5.7v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .dgnd - 0.3v to dgnd + 2.5v thermal resistance (typical) ? ja (c/w) ? jc (c/w) 48 ld cqfp r48.a (notes 3, 5) . . . . . . . . . 36.5 3 48 ld cqfp r48.b (notes 4, 6) . . . . . . . . . 19 1.3 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+145c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions avdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . agnd + 3v to 5.5v dvdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dgnd + 3v to 5.5v pvinx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pgndx + 3v to 5.5v avdd - agnd, dvdd - dgnd . . . . . . . . . . . . . . . . . . . . pvinx - pgndx 0.1v signal pins (note 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . agnd to avdd digital control pins (note 9) . . . . . . . . . . . . . . . . . . . . . . . . . .dgnd to dvdd ref, ss. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . internally set gnd, tdi, tdo, tpgm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dgnd i lxx (t j +145c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0a to 1.0a ambient temperature range . . . . . . . . . . . . . . . . . . . . . . .-55c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 3. ? ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 4. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379. 5. for ? jc , the ?case temp? location is the center of the package underside. 6. for ? jc , the ?case temp? location is the center of the exposed metal heatsink on the package underside. 7. en, fb, porsel and ref pins. 8. m/s, sync, tdi, tdo and zap pins. 9. for operation in a heavy ion environment tested at let = 86.4 mev?cm 2 /mg with +125c (t c ). electrical specifications unless otherwise noted, v in = avdd = dvdd = pvinx = en = m/s = 3v or 5.5v; gnd = agnd = dgnd = pgndx = tdi = tdo = zap = 0v; fb = 0.65v; porsel = v in for 4.5v v in 5.5v and gnd for v in < 4.5v, sync = lxx = open circuit; pgood is pulled up to v in with a 1k ? resistor; ref is bypassed to gnd with a 220nf capacitor; ss is bypassed to gnd with a 100nf capacitor; i out = 0a; t a = t j = +25c. (note 12). boldface limits apply over the operating temperatur e range, -55c to +125c; over a total iodizing dose of 100krad(si) with exposure at a high dose rate of 50 - 300krad(si)/s; and over a total io dizing dose of 50krad(si) with exposure at a low dose rate of <10mrad(si)/s. parameter test conditions min (note 13) typ max (note 13) units power supply operating supply current v in = 5.5v (note 10) 40 65 ma v in = 3.6v (note 10) 25 45 ma shutdown supply current v in = 5.5v, en = gnd (note 11) 6 12 ma v in = 3.6v, en = gnd (note 11) 3 6 ma output voltage reference voltage tolerance 0.594 0.6 0.606 v output voltage tolerance v out = 0.8v to 2.5v for v in = 4.5v to 5.5v, v out = 0.8v to 2.5v for v in = 3v to 3.6v, i out = 0a to 6a (notes 14, 15) -2 0 2 % feedback (fb) input leakage current v in = 5.5v, v fb = 0.6v -1 0 1 a pwm control logic oscillator accuracy 0.85 1 1.15 mhz
ISL70001SEH, isl70001srh 9 fn7956.2 february 24, 2014 submit document feedback external oscillator range 0.8 1 1.2 mhz minimum lxx on time v in = 5.5v, test mode 110 150 ns minimum lxx off time v in = 5.5v, test mode 40 100 ns minimum lxx on time v in = 3v, test mode 150 210 ns minimum lxx off time v in = 3v, test mode 50 100 ns master/slave (m/s) input voltage input high threshold v in - 0.5 1.3 v input low threshold 1.2 0.5 v master/slave (m/s) input leakage current v in = 5.5v, m/s = gnd or v in -1 0 1 a synchronization (sync) input voltage i nput high threshold, m/s = gnd 2.3 1.7 v input low threshold, m/s = gnd 1.5 1 v synchronization (sync) input leakage current v in = 5.5v, m/s = gnd, sync = gnd or v in -1 0 1 a synchronization (sync) output voltage v in - v oh @ i oh = -1ma 0.15 0.4 v v ol @ i ol = 1ma 0.15 0.4 v power blocks upper device r ds(on) v in = 3v, 0.4a per power block, test mode (note 15) 122 215 346 m ? lower device r ds(on) v in = 3v, 0.4a per power block, test mode (note 15) 77 146 236 m ? lxx output leakage v in = 5.5v, en = lxx = gnd, single lxx output -1 0a v in = 5.5v, en = gnd, lxx = v in , single lxx output 0 15 a deadtime within a single po wer block or between power blocks (note 15) 1.7 5ns efficiency v in = 3.3v, v out = 1.8v, i out = 3a 90 % v in = 5v, v out = 2.5v, i out = 3a 92 % power-on reset por select (porsel) input high threshold v in - 0.5 1.4 v input low threshold 1.2 0.5 v por select (porsel) input leakage current v in = 5.5v, porsel = gnd or v in -1 0 1 a vin por rising threshold, porsel = v in 4.1 4.25 4.45 v hysteresis, porsel = v in 225 325 425 mv rising threshold, porsel = gnd 2.65 2.8 2.95 v hysteresis, porsel = gnd 90 175 260 mv enable (en) input voltage rising/falling threshold 0.56 0.6 0.64 v enable (en) input leakage current v in = 5.5v, en = gnd or v in -3 0 3 a enable (en) sink current en = 0.3v 6.4 11 16.6 a soft-start soft-start source current ss = gnd 20 23 27 a soft-start discharge on-resistance 2.2 4.7 ? electrical specifications unless otherwise noted, v in = avdd = dvdd = pvinx = en = m/s = 3v or 5.5v; gnd = agnd = dgnd = pgndx = tdi = tdo = zap = 0v; fb = 0.65v; porsel = v in for 4.5v v in 5.5v and gnd for v in < 4.5v, sync = lxx = open circuit; pgood is pulled up to v in with a 1k ? resistor; ref is bypassed to gnd with a 220nf capacitor; ss is bypassed to gnd with a 100nf capacitor; i out = 0a; t a = t j = +25c. (note 12). boldface limits apply over the operating temperatur e range, -55c to +125c; over a total iodizing dose of 100krad(si) with exposure at a high dose rate of 50 - 300krad(si)/s; and over a total io dizing dose of 50krad(si) with exposure at a low dose rate of <10mrad(si)/s. (continued) parameter test conditions min (note 13) typ max (note 13) units
ISL70001SEH, isl70001srh 10 fn7956.2 february 24, 2014 submit document feedback soft-start discharge time 256 clock cycles power-good signal rising threshold v fb as a% of v ref , test mode 107 111 115 % rising hysteresis v fb as a% of v ref , test mode 2 3.5 5 % falling threshold v fb as a% of v ref , test mode 85 89 93 % falling hysteresis v fb as a% of v ref , test mode 2 3.5 5 % power-good drive v in = 3v, pgood = 0.4v, en = gnd 7.3 8.2 ma power-good leakage v in = pgood = 5.5v 0.001 1 a protection features undervoltage monitor undervoltage trip threshold v in = 3v, v fb as a% of v ref , test mode 71 75 79 % undervoltage recovery threshold v in = 3v, v fb as a% of v ref , test mode 84 88 92 % overcurrent monitor overcurrent trip level lx4 power block, test mode, (note 16) 1.3 1.9 2.5 a overcurrent or short-circuit duty-cycle v in = 3v, ss interval = 200s, test mode, fault interval divided by hiccup interval 0.8 5 % notes: 10. l = 1h connected to lx 11. 1k ? pgood pull-up resistor is not populated. 12. typical values shown are not guaranteed. guaran teed min/max values are provided in the smd. 13. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 14. limits do not include tolerance of external feedback resistors. the 0a to 6a output current range may be reduced by minimum lxx on time and minimum lxx off time specifications. 15. limits established by characterization or analysis and are not production tested. 16. during an output short-circuit, peak current through the powe r block(s) can continue to build beyond the overcurrent trip le vel by up to 3a. with all six power blocks connected, peak current thro ugh the power blocks and output inductor could reach (6 x 2.5a) + 3a = 18a. the ou tput inductor must support this peak current without saturating. electrical specifications unless otherwise noted, v in = avdd = dvdd = pvinx = en = m/s = 3v or 5.5v; gnd = agnd = dgnd = pgndx = tdi = tdo = zap = 0v; fb = 0.65v; porsel = v in for 4.5v v in 5.5v and gnd for v in < 4.5v, sync = lxx = open circuit; pgood is pulled up to v in with a 1k ? resistor; ref is bypassed to gnd with a 220nf capacitor; ss is bypassed to gnd with a 100nf capacitor; i out = 0a; t a = t j = +25c. (note 12). boldface limits apply over the operating temperatur e range, -55c to +125c; over a total iodizing dose of 100krad(si) with exposure at a high dose rate of 50 - 300krad(si)/s; and over a total io dizing dose of 50krad(si) with exposure at a low dose rate of <10mrad(si)/s. (continued) parameter test conditions min (note 13) typ max (note 13) units
ISL70001SEH, isl70001srh 11 fn7956.2 february 24, 2014 submit document feedback functional description the ISL70001SEH, isl70001srh are monolithic, fixed frequency, current-mode synchron ous buck regulators with user configurable power blocks. two devices can be used to provide a total dc/dc solution for fpgas, cplds, dsps and cpus. the ISL70001SEH, isl70001srh utilize peak current-mode control with integrated compensa tion and switches at a fixed frequency of 1mhz. two device s can be synchronized 180 out-of-phase to reduce input rms ripple current. these attributes reduce the number and size of external components required, while providing excellent output transient response. the internal synchronous power switches are optimized for high efficiency and good thermal performance. the chip features a comparator ty pe enable input that provides flexibility. it can be used for simple digital on/off control or, alternately, can provide undervoltage lockout capability by using two external resistors to precisel y sense the level of an external supply voltage. a power-good signal indicates when the output voltage is within 11% typical of the nominal output voltage. regulator start-up is controlled by an analog soft-start circuit, which can be adjusted from approximately 2ms to 200ms by using an external capacitor. the ISL70001SEH, isl70001srh in corporate fault protection for the regulator. the protection circ uits include input undervoltage, output undervoltage, and output overcurrent. power blocks the power output stage of the regulator consists of six 1a capable power blocks that are paralleled to provide full 6a output current capability. the block diagram in figure 5 shows a top level view of the individual power blocks. each power block has a power supply input pin, pvinx, a phase output pin, lxx, and a power supply ground pin, pgndx. all pvinx pins must be connected to a common power supply rail and all pgndx pins must be connected to a common ground. lxx pins should be connected to the output inductor based on the required load current, but must include the lx4 pin. for example, if 3a of output current is ne eded, any three lxx pins can be connected to the inductor as long as one of them is the lx4 pin. the unused lxx pins should be left unconnected. connecting all six lxx pins to the output inductor provides a maximum 6a of output current. see the ?typical application schematic? on page 6 for pin connection guidance. a scaled pilot device associated with each power block provides current feedback. power block 4 contains the master pilot device and this is why it must be connected to the output inductor. main control loop during normal operation, the inte rnal top power switch is turned on at the beginning of each clock cycle. current in the output inductor ramps up until the curr ent comparator trips and turns off the top power mosfet. the bottom power mosfet turns on and the inductor current ramps down for the rest of the cycle. the current comparator compares the output current at the ripple current peak to a current pilot. the error amplifier monitors v out and compares it with an in ternal reference voltage. the output voltage of the error amplif ier drives a proportional current to the pilot. if v out is low, the current level of the pilot is increased and the trip off current le vel of the output is increased. the increased output current raises v out until it is in agreement with the reference voltage. output voltage selection the output voltage can be adjust ed using an external resistor divider as shown in figure 6. r t should be selected as 1k ?? to mitigate see. r t should be shunted by a 4.7nf ceramic capacitor, c c , to mitigate see and to improve loop stability margins. the ref pin should be bypassed to agnd with a 220nf ceramic capacitor to mitigate see. it should be noted that no current (s ourcing or sinking) is available from the ref pin. r b can be determined from equation 3. the designer can configure the output voltage from 0.8v to 85% of the input voltage. switching frequency/synchronization the ISL70001SEH, isl70001srh fe ature an internal oscillator running at a fixed frequency of 1mhz 15% over recommended operating conditions. the regulator can be configured to run from the internal oscillator or can be synchronized to another ISL70001SEH, isl70001srh or a see hardened external clock with a frequency range of 1mhz 20%. to run the regulator from the internal oscillator, connect the m/s pin to dvdd. in this case, the output of the internal oscillator appears on the sync pin. to synchronize the regulator to the sync output of another regulator or to a see hardened external power block 6 pgnd6 power block 5 power block 4 power block 1 power block 2 power block 3 pvin6 pgnd5 pvin5 pgnd4 pvin4 pgnd1 pvin1 pgnd2 pvin2 pgnd3 pvin3 figure 5. power block diagram lx2 lx1 lx3 lx6 lx5 lx4 figure 6. output voltage selection fb c out l out v out lxx r t r b v ref error amplifier ref c ref - + c c v ref = 0.6v c ref = 220nf r t = 1k c c = 4.7nf r b r t v ref v out v ref ? ------------------------------- - ? = (eq. 3)
ISL70001SEH, isl70001srh 12 fn7956.2 february 24, 2014 submit document feedback clock, connect the m/s pin to dgnd. in this case, the sync pin is an input that accepts an extern al synchronizing signal. when synchronizing multiple devices, slave regulators are synchronized 180 out-of-phase wi th respect to the sync output of a master regulator or to an external clock. operation initialization the ISL70001SEH, isl70001srh initialize based on the state of the power-on reset (por) monitor of the pvinx inputs and the state of the en input. successful initialization prompts a soft-start interval, and the regulator begins slowly ramping the output voltage. once the comman ded output voltage is within the proper window of operation, the power-good signal changes state from low-to-high, indicating proper regulator operation. power-on reset the por circuitry prevents the controller from attempting to soft-start before sufficient bias is present at the pvinx pins. the por threshold of the pvinx pi ns is controlled by the porsel pin. for a nominal 5v supply voltage, porsel should be connected to dvdd. for a nominal 3.3v supply voltage, porsel should be connected to dgnd. for nominal supply voltages between 5v and 3.3v, porsel should be connected to dgnd. the por rising and falling threshol ds are shown in the ?electrical specifications? table on page 9. hysteresis between the rising and falling thresholds ensures that small perturbations on pvinx seen during turn-on/turn-off of the regulator do not cause inadvertent turn-off/turn-on of the regulator. when the pvinx pins are below the por rising threshold, the internal synchronous power mosfet switches are turned off, and the lxx pins are held in a high-impedance state. enable and disable after the por input requirement is met, the ISL70001SEH, isl70001srh remains in shutdo wn until the voltage at the enable input rises above the enable threshold. figure 7 shows the enable circuit features a compar ator type input. in addition to simple logic on/off control, the enable circuit allows the level of an external voltage to precisely gate the turn-on/turn-off of the regulator. an internal i en current sink with a typical value of 11a is only active when the vo ltage on the en pin is below the enable threshold. the current sink pulls the en pin low. as v in2 rises, the enable level is not set exclusively by the resistor divider from v in2 . with the current sink active, th e enable level is defined by equation 4. r1 is the resistor from the en pin to v in2 and r2 is the resistor from the en pin to the agnd pin. once the voltage at the en pin reaches the enable threshold, the i en current sink turns off. with the part enabled and the i en current sink off, the disable level is set by the resistor divider. the disable level is defined by equation 5. the difference between the enable and disable levels provide adjustable hysteresis so that noise on v in2 does not interfere with the enabling or disabling of the regulator. to mitigate see, the en pin should be bypassed to the agnd pin with a 10nf ceramic capacitor . soft-start once the por and enable circuits are satisfied, the regulator initiates a soft-start. figure 8 shows that the soft-start circuit clamps the error amplifier referenc e voltage to the voltage on an external soft-start capacitor connected to the ss pin. v enable v r 1 r1 r2 ------- + ? i en r1 ? + = (eq. 4) figure 7. enable circuit - + v r en pvinx v in1 por logic v in2 r1 r2 i en enable comparator c en v r = 0.6v i en = 11a c en = 10nf v disable v r 1 r1 r2 ------- + ? = (eq. 5) figure 8. soft-start circuit - + v ref fb pwm logic i ss error amplifier ref c ref v out r t r b + ss c ss v ref = 0.6v i ss = 23a r d r d = 2.2 ?
ISL70001SEH, isl70001srh 13 fn7956.2 february 24, 2014 submit document feedback the soft-start capacitor is charged by an internal i ss current source. as the soft-start capacitor is charged, the output voltage slowly ramps to the set point determined by the reference voltage and the feedback network. once the voltage on the ss pin is equal to the internal reference voltage, the soft-start interval is complete. the controlled ramp of the output voltage reduces the in-rush current during start-up. the soft-start output ramp interval is defined in equa tion 6 and is adjustable from approximately 2ms to 200ms. the value of the soft-start capacitor, c ss , should range from 8.2nf to 8.2f, inclusive. the peak in-rush current can be computed from equation 7. the soft-start interval should be long enough to ensure that the peak in-rush current plus the peak outp ut load current does not exceed the overcurrent trip level of the regulator. the soft-start capacitor is immediately discharged by a 2.2 ?? resistor whenever por conditions are not met or en is pulled low. the soft-start discharge time is equal to 256 clock cycles. power-good the power-good (pgood) pin is an open-drain logic output that indicates when the output voltag e of the regulator is within regulation limits. the power-good pin pulls low during shutdown and remains low when the controller is enabled. after a successful soft-start, the pgoo d pin releases, and the voltage rises with an external pull-up resistor. the power-good signal transitions low immediately wh en the en pin is pulled low. the power-good circuitry monitors the fb pin and compares it to the rising and falling thresholds shown in the ?electrical specifications? table on page 10. if the feedback voltage exceeds the typical rising limit of 111% of the reference voltage, the pgood pin pulls low. the pgood pin continues to pull low until the feedback voltage falls to a typical of 107.5% of the reference voltage. if the feedback voltage drops below a typical of 89% of the reference voltage, the pgood pin pulls low. the pgood pin continues to pull low until the feedback voltage rises to a typical 92.5% of the reference voltage. the pgood pin then releases and signals the return of the output voltage to within the power-good window. the pgood pin can be pulled up to any voltage from 0v to 5.5v, independently from the supply voltage. the pull-up resistor should have a nominal value from 1k ? to 10k ? . the pgood pin should be bypassed to dgnd, with a 10nf ceramic capacitor to mitigate see. fault monitoring and protection the ISL70001SEH, isl70001srh ac tively monitor output voltage and current to detect fault conditions. fault conditions trigger protective measures to prevent damage to the regulator and external load device. undervoltage protection a hysteretic comparator monitors the fb pin of the regulator. the feedback voltage is compared to an undervoltage threshold that is a fixed percentage of the reference voltage. once the comparator trips, indicating a valid undervoltage condition, a 3-bit undervoltage counter increments. the counter is reset if the feedback voltage rises back above the undervoltage threshold, plus a specified amount of hysteresis outlined in the ?electrical specifications? table on page 10. if the 3-bit counter overflows, the undervoltage protection logic shuts down the regulator. after the regulator shuts down, it enters a delay interval equivalent to the soft-start interval, which allows the device to cool. the undervoltage counter is reset when the device enters the delay interval. the protection logic initiates a normal soft-start once the delay interval ends. if the output successfully soft-starts, the power-good signal goes high, and normal operation continues. if undervolta ge conditions continue to exist during the soft-start interval, the undervoltage counter must overflow before the regulator shuts down again. this hiccup mode continues indefinitely until the output soft-starts successfully. overcurrent protection a pilot device integrated into the pmos transistor of power block 4 samples current each cycle. this current feedback is scaled and compared to an overcurrent thre shold based on the number of power blocks connected. each a dditional power block connected beyond power block 4 increases the overcurrent limit by 2a. for example, if three power blocks are connected, the typical current limit threshold would be 3 x 2a = 6a. if the sampled current exceeds th e overcurrent threshold, a 3-bit overcurrent counter increments by one lsb. if the sampled current falls below the threshold before th e counter overflows, the counter is reset. once the overcurrent counter reaches 111, the regulator shuts down. after the regulator shuts down, it enters a delay interval, equivalent to the soft-start interval, which allows the device to cool. the overcurrent counter is reset when the device enters the delay interval. the protection logic initiates a normal soft-start once the delay interval ends. if the output successfully soft-starts, the power-good signal goes high, and normal operation continues. if overcurrent conditions continue to exist during the soft-start interval, the overcurrent counter must overflow before the regulator shuts down the output again. this hiccup mode continues indefinite ly until the output soft-starts successfully. note: to prevent severe negative ringing that can disturb the overcurrent counter, it is recommended that a schottky diode of appropriate rating be added from the lxx pins to the pgndx pins. feedback loop compensation to reduce the number of external components and to simplify the process of determining compensation components, the ISL70001SEH, isl70001srh buck regulators have an internally compensated error amplifier. due to the current loop feedback in peak current mode control, the modulator has a single pole response with -20db slope at a frequency determined by the load (equation 8): t ss c ss v ref i ss ------------ - ? = (eq. 6) i inrush c out v out t ss ------------ - ? = (eq. 7) f po 1 2 ? r o c out ?? ------------------------------------ - = (eq. 8)
ISL70001SEH, isl70001srh 14 fn7956.2 february 24, 2014 submit document feedback where r o is load resistance and c out is the output load capacitance. for this type of modulator, a type 2 compensation circuit is usually sufficient. figure 9 shows a type 2 amplifie r and its response, along with the responses of the current mode modulator and the converter. the type 2 amplifier, in addition to the pole at origin, has a zero-pole pair that causes a fl at gain region at frequencies between the zero and the pole (equations 9 and 10). zero frequency and amplifier high-f requency gain were chosen to satisfy typical applications. the crossover frequency will appear at the point where the modulator attenuation equals the amplifier high frequency gain. the only task that the system designer has to complete is to specify the output filter capacitors to position the load main pole somewhere within one decade lower than the amplifier zero fr equency. equation 13 on page 13 approximates the amount of capa citance needed to achieve an optimal pole location depending on the number of lxx pins connected. with this type of compensation, plenty of phase margin is easily achieved due to zero-pole pair phase ?boost?. conditional stability may occur only when the main load pole is positioned too much to the left side on the frequency axis due to excessive output filter capacitance. in this case, the esr zero placed within the 1.2khz to 30k hz range gives some additional phase ?boost?. some phase boos t is also be achieved by connecting the recommended capacitor c c in parallel with the upper resistor r t of the divider that sets the output voltage value, as demonstrated in figure 6. component selection guide this design guide is intended to provide a high-level explanation of the steps necessary to create a power converter. it is assumed the reader is familiar with many of the basic skills and techniques referenced in the followi ng. in addition to this guide, intersil provides a complete ev aluation board that includes schematic, bom, and an exampl e pcb layout (see ordering information table on page 3). output filter design the output inductor and the outp ut capacitor bank together to form a low-pass filter responsible for smoothing the pulsating voltage at the phase node. the filter must also provide the transient energy until the regulator can respond. since the filter has low bandwidth relative to the switching frequency, it limits the system transient response. the output capacitors must supply or sink current while the current in the output inductor increases or decreases to meet the load demand. output capacitor selection the critical load parameters in choosing the output capacitors are the maximum size of the load step (distep), the load-current slew rate (di/dt), and the ma ximum allowable output voltage deviation under transient loading (dvmax). capacitors are characterized according to their capacitance, equivalent series resistance (esr) and equivale nt series inductance (esl). at the beginning of a load transien t, the output capacitors supply all of the transient current. the output voltage initially deviates by an amount approximated by the voltage drop across the esl. as the load current increases, the voltage drop across the esr increases linearly until the load current reaches its final value. neglecting the contribution of inductor current and regulator response, the output voltage init ially deviates by an amount shown in equation 11. the filter capacitors selected must have sufficiently low esl and esr, such that the total output voltage deviation is less than the maximum allowable ripple. most capacitor solutions rely on a mixture of high frequency capacitors with relatively low capacitance in combination with bulk capacitors having high capacitance but larger esr. minimizing the esl of the high-frequency capacitors allows them to support the output voltage as the current increases. minimizing the esr of the bulk capacitors allows them to supply the increased current with less output voltage deviation. ceramic capacitors with x7r dielectric are recommended. alternately, a combination of lo w esr solid tantalum capacitors and ceramic capacitors with x7r dielectric may be used. the esr of the bulk capacitors is responsible for most of the output voltage ripple. as the bulk capacitors sink and source the inductor ac ripple current, a voltage, v p-p(max) , develops across the bulk capacitor according to equation 12. another consideration in selecting the output capacitors is loop stability. the total output capacitance sets the dominant pole of the pwm. because the isl7 0001seh, isl70001srh use integrated compensation techniques , it is necessary to restrict the output capacitance in order to optimize loop stability. the recommended load capacitance can be estimated using equation 13. figure 9. feedback loop compensation r1 r2 c1 c2 f po f z f p f c modulator ea converter type 2 ea g ea = 25.1db f z 1 2 ? r 2 c 1 ?? ----------------------------- - 8.6khz == (eq. 9) f p 1 2 ? r 1 c 2 ?? ----------------------------- - 546khz == (eq. 10) ? v max esl di dt ----- ? esr ? i step ? ?? + ? (eq. 11) v p-p(max) esr v in v out ? ?? v out l out f s ? v in ? ---------------------------------------------- ? = (eq. 12) c out 75 ? f number of lxx pins connected 1.8v v out ------------ - ? ? = (eq. 13)
ISL70001SEH, isl70001srh 15 fn7956.2 february 24, 2014 submit document feedback another stability requirement on the selection of the output capacitor is that the ?esr zero? (f zesr ) be placed at 60khz to 90khz. this range is set by an internal, single compensation zero at 8.6khz. this esr zero location contributes to increased phase margin of the control loop; therefore (equation 14): in conclusion, the output capaci tors must meet three criteria: 1. they must have sufficient bulk capacitance to sustain the output voltage during a load transient while the output inductor current is slewing to the value of the load transient. 2. the esr must be sufficiently low to meet the desired output voltage ripple due to the output inductor current. 3. the esr zero should be placed, in a rather large range, to provide additional phase margin. output inductor selection once the output capacitors are selected, the maximum allowable ripple voltage, v p-p(max) , determines the lower limit on the inductance as shown in equation 15. since the output capacitors are supplying a decreasing portion of the load current while the regulato r recovers from the transient, the capacitor voltage becomes slightly depleted. the output inductor must be capable of assuming the entire load current before the output voltage decreases more than ? v max . this places an upper limit on inductance. equation 16 gives the upper limit on output inductance for the case when the trailing edge of the current transient causes a greater output voltage deviat ion than the leading edge. equation 17 addresses the leadin g edge. normally, the trailing edge dictates the inductance selection because duty cycles are usually <50%. nevertheless, both inequalities should be evaluated, and inductance shou ld be governed based on the lower of the two results. in each equation, l out is the output inductance, c out is the total output capacitance, and ? i l(p-p) is the peak-to-peak ripple current in the output inductor. the other concern when selecting an output inductor is to ensure there is adequate slope compen sation when the regulator is operated above 50% duty cycle. since the internal slope compensation is fixed, output inductance should satisfy equation 18 to ensure this requirement is met. input capacitor selection input capacitors are responsible for sourcing the ac component of the input current flowing into the switching power devices. their rms current capacity must be sufficient to handle the ac component of the current drawn by the switching power devices, which is related to duty cycle. the maximum rms current required by the regulator is closely approximated by equation 19. the important parameters to consider when selecting an input capacitor are the voltage rating and the rms ripple current rating. for reliable operation, select capacitors with voltage ratings at least 1.5x greater than the maximum input voltage. the capacitor rms ripple current rating should be higher than the largest rms ripple current required by the circuit. ceramic capacitors with x7r dielectric are recommended. alternately, a combination of lo w esr solid tantalum capacitors and ceramic capacitors with x7r dielectric may be used. the ISL70001SEH, isl70001srh require a minimum effective input capacitance of 100f for stable operation. derating current capability most space programs issue specific derating guidelines for parts, but these guidelines take the pedi gree of the part into account. for instance, a device built to mil-prf-38535, such as the isl70001, is already heavily de rated from a current density standpoint. however, a mil-temp or commercial ic that is up-screened for use in space appl ications may need additional current derating to ensure reliable operation because it was not built to the same standards as the isl70001. figure 10 shows the maximum average output current of the isl70001 with respect to junction temperature. these plots take into account the worst-case current share mismatch in the power blocks and the current density requirement of mil-prf-38535 (< 2 x 10 5 a/cm 2 ). the plot clearly shows that the isl70001 can handle 12.1a at +125c from a worst-case current density standpoint, but the part is limite d to 7.8a because that is the lower limit of the current limit threshold with all six power blocks connected. esr 1 2 ? f zesr ?? c out ?? ---------------------------------------------- = (eq. 14) l out esr v in v out ? ?? v out f s v in ? v p-p(max) ? ------------------------------------------------- - ? ? (eq. 15) l out 2 c out v out ?? ? i step ?? 2 --------------------------------------- ? v max ? i l(p-p) esr ? ?? ? ? (eq. 16) l out 2c out ? ? i step ?? 2 -------------------------- ? v max ? i l(p-p) esr ? ?? ? v in v o ut ? ?? ?? ? (eq. 17) l out 4.32 ? h number of lxx pins connected ------------------------------------------------------------------------------------------- ? (eq. 18) i rms max ?? v out v in ----------------- i out max ?? 2 1 12 ------ v in v out ? l out f s ? ---------------------------------- v out v in ----------------- ? ?? ?? ?? 2 ? + ?? ?? ?? ? = (eq. 19) 12.14 10.18 8.57 7.25 6.16 5.3 4 5 6 7 8 9 10 11 12 13 120 125 130 135 140 145 150 155 junction temperature (c) minimum ocp level = 7.8a 6a @ +146c maximum average current for 0.1% failures at 100,000 hours (a) figure 10. current vs temperature
ISL70001SEH, isl70001srh 16 fn7956.2 february 24, 2014 submit document feedback pcb design pcb design is critical to high-frequency switching regulator performance. careful component placement and trace routing are necessary to reduce voltage spikes and minimize undesirable voltage drops. selection of a suitable thermal interface material is also requir ed for optimum heat dissipation and to provide lead strain relief. see table 1 on page 18 for layout x-y coordinates. pcb plane allocation four layers of 2-ounce copper are recommended. layer 2 should be a dedicated ground plane with all critical component ground connections made with vias to this layer. layer 3 should be a dedicated power plane split between the input and output power rails. layers 1 and 4 should be used primarily for signals but can also provide additional power and ground islands, as required. pcb component placement components should be placed as close as possible to the ic to minimize stray inductance an d resistance. pr ioritize the placement of bypass capacitors on the pins of the ic in the order shown: ref, ss, avdd, dvdd, pvinx (high frequency capacitors), en, pgood, pvinx (bulk capacitors). locate the output voltage resistive divider as close as possible to the fb pin of the ic. the top leg of the divider should connect directly to the pol (point of load), and the bottom leg of the divider should connect directly to agnd. the junction of the resistive divider should conne ct directly to the fb pin. locate a schottky clamp diode as close as possible to the lxx and pgndx pins of the ic. a smal l series r-c snubber connected from the lxx pins to the pgndx pins may be used to damp high frequency ringing on the lxx pins , if desired, see figure 11. pcb layout use a small island of copper to connect the lxx pins of the ic to the output inductor on layers 1 and 4. to minimize capacitive coupling to the power and ground planes, void the copper on layers 2 and 3 adjacent to the island. place most of the island of layer 4 to minimize the amount of copper that must be voided from the ground plane (layer 2). keep all other signal traces as short as possible. for an example layout, see an1518 . thermal management for ceramic package for optimum thermal performance, place a pattern of vias and a thermal land on the top layer of the pcb directly underneath the ic. connect the vias to the plane, which serves as a heatsink. to ensure good thermal contact, thermal interface material such as a sil-pad or thermally conductive epoxy should be used to fill the gap between the vias and the bo ttom of the ceramic package. lead strain relief the package leads protrude from the bottom of the package and the leads need forming to provide strain relief. on the ceramic bottom package r48.a, the sil-pad or epoxy maybe be used to fill the gap left between the pcb board and the bottom of the package when lead forming is completed. on the heat sink option of the package, r48.b, th e lead forming should be made so that the bottom of the heat sink and the formed leads are flush. heat sink mounting guidelines the r48.b package option has a heat sink mounted on the underside of the package. the following jesd51-5 guidelines may be used to mount the package: 1. place a thermal land on the pcb under the heat sink. 2. the land should be approximately the same size as to 1mm larger than the 9x9mm heat sink. 3. place an array of thermal vias below the thermal land. - via array size: ~8x8=64 thermal vias - via diameter: ~0.3mm drill diameter with plated copper on the inside of each via. - via pitch: ~1.2mm. - vias should drop to and contac t as much buried metal area as feasible to provide the best thermal relief. heat sink electrical potential the heat sink is electrically is olated and unbiased. the heatsink may be electrically connected to any potential, which offers the best thermal relief through co nductive mounting materials (conductive epoxy, solder, etc.) or may be left unbiased through the use of electrically non-conductive mounting materials (non-conductive epoxy, sil-pad, kapton film, etc.). figure 11. schottky diode and r-c snubber fb c out l out v out lxx r t r b v ref error amplifier ref c ref - + c c 3a r s c s pgndx
ISL70001SEH, isl70001srh 17 fn7956.2 february 24, 2014 submit document feedback weight characteristics weight of packaged device 1.602 grams typical - r48.a package 2.440 grams typical - r48.b package die characteristics die dimensions 5720m x 5830m (225.2 mils x 229.5 mils) thickness: 483m 25.4m (19.0 mils 1 mil) interface materials glassivation type: silicon oxide and silicon nitride thickness: 0.3m 0.03m to 1.2m 0.12m top metallization type: alcu (0.5%) thickness: 2.7m 0.4m substrate type: silicon isolation: junction backside finish silicon assembly related information substrate potential - package r48.a and r48.b: pgnd metal lid potential electrically isolated -package r48.a pgnd - package r48.b additional information worst case current density < 2 x 10 5 a/cm 2 transistor count 25030 layout characteristics step and repeat 5720m x 5830m connect pgnd to pgndx metallization mask layout ISL70001SEH, isl70001srh pvin1 lx1 pgnd1 pgnd2 lx2 pvin2 pvin3 sync m/s zap tdi tdo pgood ss dvdd dgnd pgnd agnd avdd ref fb en porsel pvin6 lx6 pgnd6 pgnd5 lx5 pvin5 pvin4 lx4 pgnd4 pgnd3 lx3 origin
ISL70001SEH, isl70001srh 18 fn7956.2 february 24, 2014 submit document feedback table 1. layout x-y coordinates pad name pad number x (m) y (m) dx (m) dy (m) bond wires per pad avdd 15 478 263 135 135 1 ref 16 865 263 135 135 1 fb 17 1295 263 135 135 1 en 18 1751 263 135 135 1 porsel 19 2151 263 135 135 1 pvin6 20 2838 188 521 135 3 lx6 21 3449 188 521 135 3 pgnd6 22 4060 188 521 135 3 pgnd5 23 4845 188 521 135 3 lx5 24 5449 925 135 521 3 pvin5 25 5449 1651 135 521 3 pvin4 26 5449 2263 135 521 3 lx4 27 5449 2874 135 521 3 pgnd4 28 5449 3485 135 521 3 pgnd3 29 5449 4096 135 521 3 lx3 30 5449 4745 135 521 3 pvin3 31 4941 5559 521 135 3 pvin2 32 4137 5559 521 135 3 lx2 33 3449 5559 521 135 3 pgnd2 34 2838 5559 521 135 3 pgnd1 1 2227 5559 521 135 3 lx1 2 1578 5559 521 135 3 pvin1 3 962 5559 521 135 3 sync 4 544 5559 135 135 1 m/s 5 226 5280 135 135 1 zap 6 226 4910 135 135 1 tdi 7 226 4540 135 135 1 tdo 8 226 4170 135 135 1 pgood 9 226 3777 135 135 1 ss 10 226 3425 135 135 1 dvdd 11 226 2566 135 333 2 dgnd 12 226 1538 135 333 2 pgnd 13 226 1018 135 135 1 agnd 14 226 654 135 135 1
ISL70001SEH, isl70001srh 19 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7956.2 february 24, 2014 for additional products, see www.intersil.com/en/products.html submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o the web to make sure that you have the latest revision. date revision change february 24, 2014 fn7956.2 added note 10 on page 10. added note 11 on page 10. removed msl note from the ordering information on page 2 as it is not applicable to hermetic packages. added note 2 for ordering information table on page 3. added isl70001srh throughout datasheet. page 3: added isl70001srhqf and isl70001s rhvx to the odering information table. may 20, 2013 fn7956.1 added heat sink mounting guidelines on page 16. added ?weight characteristics? on page 17. added label ?origin? to metallization mask layout on page 17. may 6, 2013 page 3, ordering information table: removed th e word "(heatsink)" under the first column, and added to rows 2 & 6 in the fourth column "48 ld cqfp with heatsink?. page 8, thermal information table: changed note 6, from removed exposed metal pad to exposed metal heatsink. may 3, 2013 updated ordering information table on page 3 as follow: added isl7000srhvf. added ?heatsink? to help distinguish between the two package types. thermal re sistance on page 8 as follow: changed note 3 from ?low? to ?high? effective? thermal conductivity test board type and added note 4 ?direct attach?. may 2, 2013 page 2: added ISL70001SEHvfe, ISL70001SEHfe/proto parts to ordering information table and added package dwg# column to table. added pod: r48.a and r48. november 30, 2011 fn7956.0 initial release
ISL70001SEH, isl70001srh 20 fn7956.2 february 24, 2014 submit document feedback package outline drawing r48.a 48 ceramic quad flatpack package (cqfp) rev 3, 10/12 top view side view note: 1. all dimensions are in inches (millimeters). 0.015 (0.38) 1.118 (28.40) 0.015 (0.38) min 1.080 (27.43) 0.572 (14.53) 0.555 (14.10) pin 1 index area 0.008 (0.20) 1.118 (28.40) 1.080 (27.43) 0.040 (1.02) bsc 0.572 (14.53) 0.555 (14.10) 0.287 (7.29) 0.253 (6.43) 0.016 (0.41) 0.009 (0.23) 0.099 (2.51) 0.076 (1.93) 0.007 (0.18) min #48 #1
ISL70001SEH, isl70001srh 21 fn7956.2 february 24, 2014 submit document feedback package outline drawing r48.b 48 ceramic quad flatpack package (cqfp) with bottom heatsink rev 0, 10/12 1.080 (27.43) 0.555 (14.10) index area pin 1 1.118 (28.40) 0.572 (14.53) 0.253 (6.43) 0.287 (7.29) 1.118 (28.40) 1.080 (27.43) 0.040 (1.016) bsc 0.012 (0.30) 0.008 (0.20) 0.572 (14.53) 0.555 (14.10) #48 #1 top view 0.013 (0.33) 0.131 (3.33) 0.042 (1.067) ref side view 0.009 (0.23) 0.105 (2.67) heatsink 0.026 (0.66) min. 2 pin 1 index area bottom view #1 #48 0.359 (9.12) heatsink 0.349 (8.87) 0.349 (8.87) 0.359 (9.12) notes: 1. all dimensions are in inches (millimeters) 2. dimension shall be measured at point of exit (beyond the meniscus) of the lead from the body.

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